Laser Detection System for HIT Tanks

A laser is a device that emits light through a process of optical amplification based on the stimulated emission of radiation. Laser is used in most organizations for different purposes. In this context, military uses of lasers include applications such as target designation and ranging, defensive c

Project Title

Laser Detection System for HIT Tanks

Project Area of Specialization

Electrical/Electronic Engineering

Project Summary

A laser is a device that emits light through a process of optical amplification based on the stimulated emission of radiation. Laser is used in most organizations for different purposes. In this context, military uses of lasers include applications such as target designation and ranging, defensive countermeasures, communications, and directed energy weapons. When the hostile targets the tank, it is necessary to detect, classify, identify and give warning of hostile laser threats aiming at the platform, in a very short time with high sensitivity. So, we need a system which can be able to: -

• Detect the laser radiations
• Decodes the radiations
• Locates the directions of laser emissions

The idea is to design an embedded system that is a pre-processing circuit to convert analog light signals into digital signals, an FPGA that can perform logical processing, a microprocessor that can control a display screen, and is an interface between logic and its execution. The pre-processing circuit will be consisting of a detector, operational amplifier & comparators to convert analog pulses into digital signals. We receive this digital signal on FPGA, these digital signals are required to be detected and processed by FPGA.

Project Objectives

The objective of this project is to: -

• Design a digital system
• Which process the digital signals
• And notify (provide result) the threat

Project Implementation Method

We will receive the pulses of 50ns on FPGA. When the pulse will receive initially its width is 6ns. In preliminary processing, it will be stretched to 50ns when it is received on FPGA. These 50 nanosecond pulses (frequency of 20MHz) can have a pulse period from 1 microsecond to 200 milliseconds. To effectively detect all the pulses, we need to design our logic on at least a 50 MHz clock for I/Os.

When these pulses will have been received on FPGA, then processing is required to: -

• Detect & indicate the pulse or pulses
• Identify & indicate the direction of pulses
• Able to receive outputs of FPGA
• Display outputs on LCD

It should be able to receive all the outputs of FPGA and display them on a 7-inch LCD.

The Processing System IP is the software interface around the Zynq® Ultrascale+™ MPSoC Processing System. The ZynqUltraScaleMPSoC family consists of a system-on-chip (SoC) style integrated processing system (PS) and a Programmable Logic (PL) unit, providing an extensible and flexible SoC solution on a single die.

The Processing System IP Wrapper acts as a logical connection between the PS and the PL while assisting you to integrate custom and embedded IPs with the processing system using the Vivado® IP integrator.

Benefits of the Project

We will implement a digital system that will detect the LASER. This project basically deploys on military Tanks to enhance the protection on the battlefield. Major features of this project are detecting the LASER radiation, decoding the radiation, locates the directions of laser emission. We will use FPGA (Xilinx) to implement this project and output will display on LCD. ZYBO board provides an SoC (System On Chip) which includes PS (Processing System) and PL (Programmable Logic) which provide efficiency and ease to achieve a high speed of real-time processing.

Technical Details of Final Deliverable

“Real-Time Processing of High-Speed Digital Signals”

The idea or requirement is to design an embedded system that is a pre-processing circuit to convert analog light signals into digital signals, an FPGA that can perform logical processing, a microprocessor that can control a display screen, and is an interface between logic and its execution. The system will consist of the following: -

The received pulses will have a pulse width of 6 nanoseconds on the incidence side and due to preprocessing electronics; will be stretched to 50 nanoseconds when they are received on the input pin of FPGA. These 50 nanosecond pulses (frequency of 20MHz) can have a pulse period from 1 microsecond to 200ms. To effectively detect all the pulses, we need to design our logic on at least a 50 MHz clock for I/Os.

These pulses are going into FPGA. FPGA pin will remain high once pulse will be received. These pulses are required to be detected & processed by the FPGA.

Now, Processing is required to detect, indicate the pulses, and identify the direction of origin in azimuth angle, which will further display on LCD.

Final Deliverable of the Project

HW/SW integrated system

Core Industry

Others

Other Industries

Core Technology

Others

Other Technologies

Sustainable Development Goals

Industry, Innovation and Infrastructure

Required Resources

If you need this project, please contact me on contact@adikhanofficial.com