VLSI design and implementation of integer transform architecture for HEVC

The generation of high multimedia data contents along with the availability of online services and transmission technologies, the world has entered into new phase of big data [1]. The main contents of this big data are new multimedia contents i.e. images and videos. This opens up new challenges and

Project Title

VLSI design and implementation of integer transform architecture for HEVC

Project Area of Specialization

Electrical/Electronic Engineering

Project Summary

The generation of high multimedia data contents along with the availability of online services and transmission technologies, the world has entered into new phase of big data [1]. The main contents of this big data are new multimedia contents i.e. images and videos. This opens up new challenges and opportunities in research of image processing and transmission. In the heart of these techniques, defined by various multimedia contents lies various image compression techniques defined by different industrial standards. High Efficiency Video Coding (HEVC) uses the integer transforms of varied sizes between 4x4 and 32x32. HEVC is the successor to Advanced Video Coding and as of 2019 is used by 43% of the video developers [2]. HEVC uses integer Discrete Cosine Transform (DCT) and Discrete Sine Transform (DST) transforms with varied block sizes between 4x4 and 32x32. The integer transforms are widely used in solving practical problems of signal processing with specific applications to video and image processing [2]. In any of the multimedia standard, transform processing is one of the important part. The objective of transform processing is to encode parts of the input data into a fewer coefficients, thereby allowing the compression to work more efficiently. DCT and DST are part of HEVC standard and expected to be part of many other future video and still image compressions algorithms [2]. There are many realizations (hardware) for these transforms, but the high requirement of high speed compression requires fast and reduced complexity design for its implementation [2]. In this project, we will work on implementing a low complexity integer transform architecture based on the Canonical Signed Digit (CSD) represented Distributed Arithmetic (DA) architecture. The advantage of the DA architecture is that along with CSD representation, it can exploit the computational redundancy within the inner product of the integer transform, giving a multiplier less implementation of hardware. The HDL (Hardware Description Language) code of the integers transforms will be written in the Verilog HDL and the architecture will be hardware implemented on Field Programmable Gate Array (FPGA). The proposed implementation will be compared with previously implemented integer transform architectures. The designed architecture is expected to be low-complexity and will alleviate the problems with handling of multimedia in big data environment.

Refrences:

[1] Shan Liu, Yao Dong, Jianping Chai, "The Evolution Model of Public Resource in Multimedia Big Data Networks", Image and Signal Processing BioMedical Engineering and Informatics (CISP-BMEI) 2018 11th International Congress on, pp. 1-6, 2018.

[2]G. J. Sullivan, J.-R. Ohm, W.-J. Han, T. Wiegand, "Overview of the High Efficiency Video Coding (HEVC) standard", IEEE Trans. Circuits Syst. Video Technol., vol. 22, pp. 1648-1667, Dec. 2012.

Project Objectives

It is well known that the Integer Transforms are widely used in solving practical problems of image processing with specific applications to video and image compression. An efficient integer transforms architecture solution is always desired for the low-power real time image processing application. In this work, we will design architecture and hardware implement a low complexity 1D Integer Transforms using the CSD represented DA architecture. The proposed designed solution and implementation will give a low complexity hardware efficient architecture for handling the multimedia in big data environment. The objective of the project are as follows

1. Design low complexity integer transform architecture using Canonical Signed Digit and Distributed Arithmetic for High Efficiency Video Coding (HEVC).
2. Write HDL code of the designed architecture and VLSI implement it on Field Programmable Gate Array.
3. Compare hardware implementation results with Matlab simulation results.

Project Implementation Method

1. 1D Integer Transform (DCT and DST) Matlab Implementation: The main objective is to understand the basics of Integer Transform. The study will include learning 1D and 2D Analog and Discrete Integer Transform. We will look in to effect of Integer Transform and Inverse Integer Transform on various 1D and 2D data and images.

2. Literature Review: In this, we will study scholarly papers, which include the latest architecture to design and implement of the Integer Transform (both DCT and DST). The aim is to have the critical analysis of the published work and know latest trends in the design and VLSI implementation of Integer Transform architectures for image processing applications.

3. HDL Coding and Simulation Integer Transform on ModelSim: In addition to learning Verilog HDL, the design and simulation phase of our project includes the installation and simulation of our design on ModelSim, a leading a multi-language HDL simulation environment by Mentor Graphics.  Multiple designs of 1D Integer Transform (supporting DCT and DST) will be simulated to verify the architecture and its performance. The implementation will be synthesized and will be re-adjusted to achieve optimal performance, accuracy and low power architecture.

4. VLSI Implementation of Integer Transform on FPGA: In the VLSI implementation, the chosen design in the simulation phase will be actually implemented in hardware. Note that, based on the initial result of the hardware implementation, the cycle can always goes back to re-design and simulation phase to readjust various parameters.

5. VLSI Implementation Testing: A number of tests will be performed on Integer Transforms architecture. We will be particularly interested in following

a. Error due to Quantization.

b. PSNR.

c. Minimum Mean Square Error.

In addition, various test results will be compared against theoretical calculated values to check accuracy of the hardware implementation.

7. Writing of Thesis: In last step, we will write down dissertation to support our VLSI design and implementation of Integer Transform. All necessary details of our designed architecture and realization will be discussed along with the future research recommendation identified during our research.

Benefits of the Project

We live in digital era, where multimedia is part of our daily routine life. The usage of internet through various cell phone and computer devices is increasing exponentially. These applications use multimedia such as images, audio, video etc., resulting in increase in demand of multimedia contents. In order to meet new requirements, we need to improve the performance of our devices as well as their storage capacity of multimedia files, which can occupy considerable space. This necessitates development of media compression techniques and its architecture to transmit efficiently the high fidelity media contents over multimedia channels. Our project’s goal is focused on current state of the art multimedia standard High Efficiency Video Coding (HEVC) and to provide an efficient architecture for transform coding block in this video compression to reduce the file size as well as to improve the performance of these standard.

Technical Details of Final Deliverable

FPGA will be used for hardware implementation of our project. Verilog HDL will be used for coding and performing simulations. Many different simulations will be performed and compared to get optimum result results.

The final deliverable will be an application specific hardware IP (Intellectual Property) block. The IP block will have following characteristics

1. Clock frequency 20MHz – 80MHz
2. Area(Slice)  minimum

. 

Final Deliverable of the Project

HW/SW integrated system

Core Industry

Telecommunication

Other Industries

Core Technology

Others

Other Technologies

Sustainable Development Goals

Industry, Innovation and Infrastructure

Required Resources

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