Efficient implementation of ciphering for wireless communication

Advanced encryption standard(AES)  is a 128-bit block cipher consisting of three types of keys i.e  128,192 and 256 bits. AES is subdivided into four main blocks i.e substitute bytes, shift rows, mix columns, and key expansion. This project consists of two main parts i.e hardware

Project Title

Efficient implementation of ciphering for wireless communication

Project Area of Specialization

Cyber Security

Project Summary

Advanced encryption standard(AES)  is a 128-bit block cipher consisting of three types of keys i.e  128,192 and 256 bits. AES is subdivided into four main blocks i.e substitute bytes, shift rows, mix columns, and key expansion. This project consists of two main parts i.e hardware and software. The software part of this project consists of programming in python and verilog meanwhile the hardware is implemented on a field-programmable gate array. Hardware is divided into four parts i.e rounding function, implementation of Feistel network, key generation, and optimization

Project Objectives

´The main objective of this project is implementation of Advanced Encryption Standard (AES) in software and hardware to encrypt sensitive data.

In this project Verilog (Hardware description language) is used to implement algorithm on Field programmable gate array (FPGA)/ASIC.

Project Implementation Method

Our project is divided into four main parts:

1-Literature review

2-Software implementation

3-Hardware implementation

4-Documentation

Literature Review:

We did overall research on the topic and have read Cryptography and Network Security which has vast information about cryptography, cryptanalysis, Feistel cipher, DES, triple DES, AES and much more. We also have been studying Verilog which is a hardware description language used for programming in FPGA/ASIC.

Software Implementation:

For software implementation python and Verilog will be used for writing the program. First coding will be done in python for our ease of understanding because in python it is easy to write, read and learn and it has English-syntax. After that the code will be written in Verilog to be implemented on FPGA.

Hardware Implementation:

Hardware implementation will be done on FPGA/ASIC.

Documentation:

Everything that we will study, work on, the problems that we will face and the how we overcame those problems would be written in our final report

Benefits of the Project

This project is divided into two main parts

1-Cryptography

2-Hardware Security

CRYPTOGRAPHY

By using cryptography we can secure a sensitive message in a way that only the person who has the key for that message would be able to interpret it. In the near future, it might be possible that almost everything will be encrypted. Numerous cryptographic processes may possibly be put on every byte of data, The need for cryptography in all walks of life is continuously increasing, with increasing data every year and the increasing key sizes used by organizations, along with multiple synchronized algorithms, to reinforce security. With every passing minute, the requirement for security and encryption of data continues to expand.

HARDWARE SECURITY

Hardware security provides a layer of security and protects data from undesirable access. Hardware security is frequently used for hardware implementations of cryptographic algorithms, in which hardware is used to improve the calculation performance and efficiency for cryptographic applications.

Current hardware security methods focus primarily on chip manufacturing, circuit design, and circuit testing, future trends will expand to include a broader range of areas in order to grant hardware active roles in system level protection.

Technical Details of Final Deliverable

During the starting months of our project literature review has been done including the theory of AES, infinite fields, cryptography and verilog. After that Python and Verilog code of the Advanced encryption standard algorithm was written. After that  Implementation of the rounding function, Feistel Network,Key Generation and optimization are to be done on a field-programmable gate array. If everything goes smoothly and according to the time period then chip making will be done of AES algorithm. Report writing will be continued alongside wiith the project

Final Deliverable of the Project

Hardware System

Core Industry

Telecommunication

Other Industries

Security

Core Technology

Others

Other Technologies

Sustainable Development Goals

Gender Equality, Decent Work and Economic Growth, Peace and Justice Strong Institutions, Partnerships to achieve the Goal

Required Resources

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