RISCV CORE SIMULATOR

Project Title

RISCV CORE SIMULATOR

Project Area of Specialization Computer ScienceProject Summary

An open source web based simulation platform for the worldwide users of the RISC-V Technology. The purpose of the simulator is to accommodate the individuals and groups that wish to test and simulate their RISC-V assembly code. RISC-V Core Simulator is embedded with a quite useful feature that will allow the user to not only test and simulate but also learn about the internal structure of the RISC-V ISA.

RISC-V is an emerging field of hardware in today’s era and for students the significant knowledge about the internal architecture of hardware was a totally new concept. In order to develop simulator of RISC V base architecture every expect of knowledge about internal working of system was required including Memory segmentation and operation, register states and execution of instructions. With the collaboration of MERL (Microprocessor and Electronic Research Lab) present in UIT which is currently involved in the design and development of the first Microcontroller chip in Pakistan based on RISC V, we were able to learn all the major concepts regarding RISC V components required for the development of the simulator. The time required to gather and study its internal architecture and how each component collaborate for execution of task limits the time for development. The development of the project is prioritized in the manner such that the user benefits must not be compromised. The design of Simulator is based on the implementation of RISC-V RV-32I architecture on Simulator.

In this project we will develop a RISC-V Core Simulator. The purpose of this simulation will be to test the code written using the ISA of RISC-V and match the output of the simulator with the gtk wave which was obtained against that same code using another software. If both outputs are same then it means that code is correct and verified. This Simulator is being designed for two main purposes first is for the verification of our Buraq IoT Core and the second is that it can also be used for educational purposes.

The end product is based on interface which is further divided into two more interfaces, one for the code in ISA of RISC-V. Then the code will be interpreted to the language which our simulator can understand and then according to ISA code written in the editor will be shown to the second interface where the user will be able to see the status of all the Registers and Memory. 

Project Objectives

The simulation is intended to test the code which has been developed using the RISC-V ISA. Simulation is essential as it helps the consumer to test whether the code that has been submitted to the editor can function on the RISC-V hardware. This offers a functional device framework that the user wants to use.

The objective of our Project is to provide a platform where they can understand about ISA of RISC V architecture and where they can program assembly codes before implementing the program on actual Hardware chip which will help people to save their time and money. Hardware chips are expensive, so its only logical and feasible that developers should first test their code on a logical interface.

This simulator provides the audience with a feature that can be quite useful for them in learning the architecture of RISC-V ISA. The simulator will decode the instruction into its binary code, distribute those bits according to the structure of the instruction type and display it on the simulator screen. This functionality can be our edge in gaining popularity over other RISC-V Simulators. Because this may be the first RISC-V Simulator that offers this kind of service.

Project Implementation Method

The Project is divided in such a way that first the GUI will be designed and then the code for the RISC-V Instruction classes and the Assembler will go hand in hand. As the application is web based so GUI will be built using HTML, CSS, JavaScript and Bootstrap. The platform to implement the back-end part of the project will be Python Django(Web Framework) to keep the simulator open-source and accessible to all.

Benefits of the Project

This Simulator will provide us with the following benefits:

1. Provide a platform for RISC-V developers to test/verify their RISC-V assembly code.
2. The Simulator is open-source anyone can modify it as per requirement.
3. This simulator is operating system independent so it will be easily available to everyone.
4. It is designed to also offer educational benefits that is user can learn about the structure of RISC-V ISA through our simulator.

Technical Details of Final Deliverable

These are the final deliverables,

Project Deliverable 1: Web based GUI built using HTML5, CSS, Bootstrap, JavaScript which will have an Editor screen, Simulator screen and Register and Memory Display.

Project Deliverable 2: Assembler and classes developed using Python and Django Framework which will be able the instructions received from the editor according to their type.   

Product Deliverable: A Web based RISC-V Simulator which will be able to interpret the instructions entered in the editor screen and provide the user with the visual display and the simulation of register and memory blocks. 

Final Deliverable of the Project Software SystemCore Industry ITOther Industries Education Core Technology OthersOther Technologies Shared Economy, OthersSustainable Development Goals Quality Education, Industry, Innovation and InfrastructureRequired Resources

Item Name	Type	No. of Units	Per Unit Cost (in Rs)	Total (in Rs)
			Total in (Rs)	34750
Pycharm Professional: The Python IDE for Professional Developers	Equipment	1	30750	30750
Web hosting	Miscellaneous	1	4000	4000