RISC-V Implementation on FPGA

As we all know, our today?s life is totally dependent on the semiconductor, from our desktop PC to our smart watches, we are not just using the technology but we also ?allow? the technology provider to use our data and the data is the most important factor in this current era. If we talk about Pakis

Project Title

RISC-V Implementation on FPGA

Project Area of Specialization

Electrical/Electronic Engineering

Project Summary

As we all know, our today’s life is totally dependent on the semiconductor, from our desktop PC to our smart watches, we are not just using the technology but we also “allow” the technology provider to use our data and the data is the most important factor in this current era. If we talk about Pakistan's space agency and defense area, it is visible that we are using the silicon of international vendors that means our country's security is at risk.

There is a solution to overcome that risk with RISC-V (Reduced-Instruction-Set Computing - Five). It is an open-source and customizable computer architecture that allows every individual to design his own processor without paying any charges.

This project is all about designing customized SoC (System on Chip), based on RISC-V. Since RISC-V is a modular ISA consisting of various standard or non-standard extensions (Multiplication/Division, Floating Point, Compressed etc.) which allows it to be used in a wide range of applications starting from small microcontrollers to a complete general purpose processor. This project is aimed to design a SoC. We will start with mapping basic single-cycle processor on Logisim, then moving it to a five-stage pipeline core along with implementation on any Hardware Description or Construction Language (HDL/HCL) and porting it on FPGA for verification and also design GPIO ,UART, Tilelink bus protocol to make it a complete SoC.

The proposed project is designed SoC using RISC-V architecture on FPGA. It includes UART,GPIOs,Tilelink bus protocol and main execution unit(CPU). SoC is based on 32-bit architecture RV32IM, where ‘I’ is the base of RISC-V and ‘M’ is multiplication standard extension.

Project Objectives

Our objective is to impart the knowledge of open source processor development to new undergraduate students to kickstart the semiconductor revolution in Pakistan. With the development of RISC-V, it is easier than ever to teach and develop technology hidden underneath silicon devices that most of us use today. We want to capacitate the youth to allow inhouse development of microprocessors/SoCs which in long term, will save us millions of rupees in royalty fees, maintenance etc. and we will be able to serve various sectors in Pakistan at a lower cost.

Project Implementation Method

METHODOLOGY:

All the tools used in this project are Open Source.

Design Phase:

After reviewing the learning materials, we will design a single-cycle processor and simulate it to verify architecture. In the second step we map the processor in HDL and emulate it on FPGA. Third step is to transform the main execution unit into a five-stage pipeline. Fourth step is to include adding peripherals to the SoC and FPGA emulation.

Implementation Phase:

For testing and verifying required results ,first we will use simulation tool which accepts verilog based designs and gives an output which can be viewed in the form of waves.

Testing Phase:
Functionality of the project will be tested by loading set of instructions or a program in memory and then we will match the generated output with the expected output of the given program on any FPGA simulation or synthesis software tool.
Evaluation Phase:

Final evaluation will be done by porting RTL design on FPGA and then perform different functions by interfacing different peripheral devices.

Benefits of the Project

Pakistan has zero percent contribution in the semiconductor industry and for reasons, we cannot ignore and overcome but with the introduction of RISC-V open-source instruction set architecture, anyone can design a microprocessor and this means that it's now easier to tap into this market and be part of this industry. Undergraduate students in our country can be a part of this industry but at the moment, there is no learning path, no proper curriculum for the students. So, we as a student are trying to create an ecosystem for other students to learn and develop the required skills. With the help of this project, we will be able to showcase and build interest in students and attract them to this field of computer engineering.

This project is very beneficial because it will give a kick start to new industry revolution in Pakistan and its a new architecture and we have to start our inhouse production before its too late like over the past years.

This project is beneficial for education as well as marketing and it will make us technology independent.  

Technical Details of Final Deliverable

The final deliverable includes an SoC with RISC-V based processor integrated inside it. It can be used in low-end embedded platforms and the education sectors. The RISC-V processor will be based on five-stage pipelining through which we have an excellent throughput.

Our final deliverable also includes this system would be running on an FPGA board, and passing RISC-V complained tests using any verification platform or framework.

Final Deliverable of the Project

HW/SW integrated system

Core Industry

Education

Other Industries

IT

Core Technology

Internet of Things (IoT)

Other Technologies

Robotics

Sustainable Development Goals

Industry, Innovation and Infrastructure

Required Resources

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