Shaheen System on Chip

Project Title

Shaheen System on Chip

Project Area of Specialization Electrical/Electronic EngineeringProject Summary

This project is aimed to pave the road of research and development for others in the field of processor designing and verification. But, firstly it is focused on the development of Pakistan's first microcontroller SoC(system on a chip) based on the RISC-V open-source ISA.

We have decided to go with RISC-V ISA because it is royalty-free and right now there is a massive industrial shift towards RISC-V. Whether it is Google, Samsung, Western Digital or many other giants of the semiconductor industry are contributing to RISC-V, but in Pakistan, there is no such movement to be a part of this ongoing R&D weave. That's why this project will open the doors to others as well.

In this project, we will be using all open source tools for design and verification. Tools include Verilator which is an open-source tool for simulating Verilog and SystemVerilog designs. We will use SystemVerilog for our project. The second part of this project is physical design and APR. for that we will use Openlane for generating GDSII files.

As this project is about designing a microcontroller so surely there is a need for an SDK for programming the microcontroller. For that, we will design a custom SDK that will include drivers for all attached peripherals like, GPIO, UART, I2C, SPI, etc.

Project Objectives

The objective of the project is to introduce semiconductor-related development like chip design, verification, etc. to undergraduate students to show that Pakistani universities are capable of developing in-house microprocessor solutions. The semiconductor industry is a multi-billion dollar industry worldwide. With the introduction of open-source instruction set architecture, called ‘RISC-V’, it is easier than ever to teach and develop microprocessors at the undergraduate level. We aim to develop a microprocessor revolution in Pakistan. Previously deemed too difficult to dive into, chip design is now an achievable task and our project will be an example of that.

We believe our project has two distinct objectives.

The first objective is to introduce the concept of chip design and development in Pakistan at a level that has never been thought of before. Teaching these concepts at an early stage in a student’s academic level will spark curiosity and will motivate them to learn more about them. Many students are not taught computer architecture at this level and this is a major loss. We aim to impart this knowledge to students to motivate them to enter the field of computer science and engineering.

Our second objective is to develop general-purpose and specialized microchips that could be used in any field or sector from industrial machines to household items. General-purpose boards could be useful to teach students the inner workings of RISC-V and software development on the RISC-V ecosystem. 

Project Implementation Method

In this project, we implement System on Chip which includes a RISC-V processor, it will be written in SystemVerilog (Hardware Descriptive Language). It has a special block for multiplication and division of floating points, and peripheral interfaces interconnect using TL-UL(Tilelink- Uncashed Lightweight) bus protocol.

All the tools used in this project are Open Source.

The RTL(Register Transfer Level) will be simulated through simulation tool iverilog and verilator and then will be synthesized through synthesis tool Yosys and mapped to Xilinx Nexys Video Artix-7 Field Programmable Gate Array(FPGA) for real-time hardware emulation and verification.

The next step is the Auto Place and Route(APR) for which we will use Openlane, an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen, Fault, and custom methodology scripts for design exploration and optimization. We will analyze all the timing violations, DRC errors, and manually resolve those errors if missed in the auto place and route.

Our software will be customized for our SoC and it will perform SoC debugging and code compilation option with an intelligent text editor. We will be using open-source platforms like eclipse IDE and FreedomSDK to fulfill the software requirements.

Benefits of the Project

Pakistan has zero percent contribution in the semiconductor industry and for reasons, we cannot ignore and overcome but with the introduction of RISC-V open-source instruction set architecture, anyone can design a microprocessor and this means that it's now easier to tap into this market and be part of this industry. Undergraduate students in our country can be a part of this industry but at the moment, there is no learning path, no proper curriculum for the students. So, we as a student are trying to create an ecosystem for other students to learn and develop the required skills. With the help of this project, we will be able to showcase and build interest in students and attract them to this field of computer engineering. 

The second thing is that Pakistan gets its processor for the very first time. We are using processors that are usually from Intel. If we see our competitors for example India, they have their processor which is known as Shakti. Our project is the hierarchy from hardware to software. Our military will be going to be strong if we have our processor.

Pakistani’s can buy a processor at a cheaper rate. Another benefit is that we have agreed to go to RISC-V ISA because it is free of royalties and there is a huge industrial change to RISC-V right now. Whether it is Google, Samsung, Western Digital or many other semiconductor industry giants are contributing to RISC-V, but there is no such trend in Pakistan to be part of this continuing R&D weave. That’s why this project would open other people’s Doors.

Technical Details of Final Deliverable

The final deliverable includes an SoC with RISC-V based processor integrated inside it. It can be used in low-end embedded platforms and the education sectors. The RISC-V processor will be based on multi-stage pipelining through which we have an excellent throughput and it will be capable of executing around 30 MIPS (Million Instructions Per Second).

Our final deliverable also includes this system would be running on an FPGA board, and passing RISC-V complained tests using any verification platform or framework, and then a final tapeout.

If we get selected in Google sponsored Efabless free fabrication shuttle program that is using SKYWATER-130nm PDK then we will be able to fabricate our SoC and get the boards of Shaheen SoC into our hands.

In term of software we will be making our custom SDK(Software Development Kit) that will have the functionality to edit the C program on an intelligent editor, code compilation through GCC that will take care of our address space mapping, and in term of debugging a program running on SoC that software provides us ease to use JTAG by enabling the GDB(GNU DeBugger) with OpenOCD (Open OnChipDebugger) feature.

At last, we have a complete suite of hardware and software that are made for each other.

Final Deliverable of the Project HW/SW integrated systemCore Industry EducationOther Industries IT , Medical , Energy , Security Core Technology Internet of Things (IoT)Other Technologies Augmented & Virtual RealitySustainable Development Goals No Poverty, Quality Education, Clean Water and SanitationRequired Resources

Item Name	Type	No. of Units	Per Unit Cost (in Rs)	Total (in Rs)
			Total in (Rs)	80000
Nexys Video Artix-7 FPGA	Equipment	1	70000	70000
Printing	Miscellaneous	3	2000	6000
Stationary	Miscellaneous	1	4000	4000