RISCV Based CNN Accelrator on FPGA

Project Title

RISCV Based CNN Accelrator on FPGA

Project Area of Specialization Shared EconomyProject Summary

RISC-V, pronounced 'Risk-Five', is a processor that's available under open, free and non-restrictive license. It has widespread industry support from chip and device makers, and is designed to be freely extensible and customizable to fit any market. In FYP we will implement 32 bit integer Architecture of RISCV extended Convolution Neural Network (CNN) acceleration based on FPGA.

Project Objectives

The fundamental objective of this project is stated as

• Implement RISC-V(32I) Architecture on FPGA
• Integrate the CNN model to RISC-V architecture
• Accelerate the CNN model for real times Problems

Project Implementation Method

The software used for implement is given as :

• • Vivado 2018.3 by Xilinx used for designing of hardware using Hardware descriptive language (HDL) and block diagrams.
  • Anaconda with python 3.7.2 is used to train and extract weight for CNN inference.
  • Keras2cpp [] by Polanski used to make model in C++ and weights from python generated model and weights.

riscv-gnu-toolchain[] used to cross-compile the C/C++ code for RISC-V based CNN accelerator.

For  hardware we need the Digilent ZedBoard Zynq-7000.

Benefits of the Project

As an advanced deep learning architecture, CNN is widely
used in various fields. However, because the algorithm is
data intensive and computationally intensive, the traditional
CPU platform cannot fully exploit the parallelism of CNN.
Pure hardware implementation CNN lacks some flexibility.
Therefore, based on the characteristics of the CNN algorithm we will designs a new CNN processor that can balance
parallelism and flexibility for the characteristics of CNN
algorithm. It can not only support the execution of general
algorithms but also significantly accelerate the CNN algorithm. Aiming at the characteristics of CNN algorithm, four custom instructions are designed and implemented to speed up convolution operation, and optimized data transfer format to facilitate improvement of convolution efficiency.

Technical Details of Final Deliverable

We use the hardware description language Verilog to implementthe design of the CNN processor. The CNN test programis written in C language. Test programs compatible with CNNprocessors are mainly implemented using custom instructions.The data of the input picture is stored in the off-chip SRAM, the weight is stored in the on-chip register, and the connection between the weight and the image is stored in the on-chip register.After compiling the CNN link written in C using the RISC-V cross-compilation tool-chain, generate an executable ELF file and manually modify the machine code to implement a binary with custom instructions.

Final Deliverable of the Project HW/SW integrated systemCore Industry ManufacturingOther Industries Education Core Technology Artificial Intelligence(AI)Other Technologies OthersSustainable Development Goals Quality EducationRequired Resources

Item Name	Type	No. of Units	Per Unit Cost (in Rs)	Total (in Rs)
			Total in (Rs)	48500
Digilent ZedBoard Zynq-7000	Equipment	1	48500	48500