RISC V enabled Floating Point Unit

Project Title

RISC V enabled Floating Point Unit

Project Area of Specialization Electrical/Electronic EngineeringProject Summary

In modern day computations, especially where analog sensors are interfaced with the computation systems, FPU is an inevitable requirement. In earlier ages integer unit of the ALU was used to carry out floating point arithmetic operations, however, this technique is gradually getting old fashioned and out of practice with advent of RISC-V ISA, which is the first ever open source ISA. This was not only the problem of Intel, AMD or other ASIC design giants but also a matter to look into for new ASIC designers as well. One such ASIC design research laboratory is Microelectronics Research Laboratory. Microelectronics Research Laboratory (MERL), for whom this project is being designed, up till this date looks toward integrating open source available FPUs in the microprocessors they design however, this usage of open source FPU despite being free, has a cost. All the open source FPUs available are not all the time in line with the specific requirements of the processor which is to be designed. Some FPUs do not have multi standard compatibility and some are not even equipped with modern day Floating point representation standard such as B-Float16, also updating the open source FPU in accordance with the specific design requirements is a tedious task to achieve.
This project aims at developing an FPU with multi standard compatibility, having all the IEEE 754 (1985) standards and Bfloat16 standard as well. The implemented design is a pipelined execution unit of FPU which is able to perform 24 RISC-V floating point instructions.

Project Objectives

Currently available open-source FPUs for RISC-V are limited, and amongst all the available none of them is in line with the design requirements of MERL, and only one of them is  reconfigurable to cover all the IEEE 754 standards. Moreover, existing FPUs are available as a black box; it is complex and tedious to add new instructions to them. To fill this gap, we will design and test a new FPU compatible with Bfloat16 and all the IEEE 754 standards.  Our aim is to support MERL (a Pakistan based organisation with an aim to develop Pakistan’s own microprocessor, MERL is providing us technical and hardware support).

Project Implementation Method

RTL:

The FPU is developed by means of Register Transfer Level. The language used for this purpose is Verilog. FPU is developed in a way that it would support Multi Format operations. 

Functional Verification:

Functional verification of this FPU is carried out via both methods.
1. Open Loop testing via verilog Testbench Method.
2. Close Loop Testing via python (cocotb).

Hardware Emulation:

Hardware emulation of the FPU is carried out by means of FPGA.

Functional verification and hardware emulation serve as the feedback to RTL on the basis of which RTL is updated and errors are resolved. 

Benefits of the Project

1. The project is First ever Undergraduate Level Designed FPU, it is RISCV enabled, compatible with all IEEE precisions and also with B-Float 16 standard.

2. The project will be used for future ASIC development in MERL, as it is easily configrable with updating design requirments of MERL.

Technical Details of Final Deliverable

1. FPU Will support all RISCV FPU instructions.
2..FPU will be pipelined for Multi Cycle instructions.
3. FPU will be compatibe with ALL IEEE 754 precisions standards, also with B-Float 16 standard, This is ensured by means of prameterization technique.

Final Deliverable of the Project HW/SW integrated systemCore Industry EducationOther IndustriesCore Technology OthersOther Technologies Shared EconomySustainable Development Goals Decent Work and Economic Growth, Industry, Innovation and InfrastructureRequired Resources

Item Name	Type	No. of Units	Per Unit Cost (in Rs)	Total (in Rs)
			Total in (Rs)	4390
Printing	Miscellaneous	30	15	450
Printing Reports	Miscellaneous	6	600	3600
Stationary	Miscellaneous	2	170	340