Domain Specific Customization for RISC-V
This is an FPGA based project which mainly aims to optimize digital accelerator hardware for CNN (convolution neural networks). It is continuation of an earlier project which implemented an accelerator but had some limitations. The main areas to have emphasis on are to improve memory traffic time op
2025-06-28 16:32:11 - Adil Khan
Domain Specific Customization for RISC-V
Project Area of Specialization Electrical/Electronic EngineeringProject SummaryThis is an FPGA based project which mainly aims to optimize digital accelerator hardware for CNN (convolution neural networks). It is continuation of an earlier project which implemented an accelerator but had some limitations. The main areas to have emphasis on are to improve memory traffic time optimization by using DMA (Direct memory access), as well as, to make architecture more generic. Lastly, if time allows, we intend to add software support to make porting CNN architectures easier.
Project Objectives-
Generic implementation of CNN accelerator on RISCV
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Optimizing memory reads/writes overhead
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Simplify porting process
Project is divided into following steps
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Develop understanding of RISCV architecture
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Develop understanding of CNN architectures
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Understand existing CNN accelerator implementation
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Improve memory read/write times by designing and implementing AXI DMA
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Implement AXI master to read/write DDR memory
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Modify AXI master to transfer arrays
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Implement complete DMA and test standalone
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Test DMA by programming from RISCV
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Improve existing CNN accelerator design to support different network sizes
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Identify current architecture’s limitations
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Design hardware to be more general
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Implement CNN using new architecture (with DMA and generic hardware)
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Improve software routines to make porting easier
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Report writing
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The design can be used as an architecture to cater needs of AI on the edge market.
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Indigenous development of processors and AI accelerators is critical for different national level products where security is important
CNN accelerator for RISCV ported on FPGA with DMA implementation and improved hardware design.
Final Deliverable of the Project HW/SW integrated systemCore Industry EducationOther IndustriesCore Technology OthersOther Technologies Artificial Intelligence(AI)Sustainable Development Goals Industry, Innovation and InfrastructureRequired Resources| Item Name | Type | No. of Units | Per Unit Cost (in Rs) | Total (in Rs) |
|---|---|---|---|---|
| Total in (Rs) | 70000 | |||
| Zedboard | Equipment | 1 | 70000 | 70000 |