Domain Specific Customization for RISC-V

This is an FPGA based project which mainly aims to optimize digital accelerator hardware for CNN (convolution neural networks). It is continuation of an earlier project which implemented an accelerator but had some limitations. The main areas to have emphasis on are to improve memory traffic time op

2025-06-28 16:32:11 - Adil Khan

Project Title

Domain Specific Customization for RISC-V

Project Area of Specialization Electrical/Electronic EngineeringProject Summary

This is an FPGA based project which mainly aims to optimize digital accelerator hardware for CNN (convolution neural networks). It is continuation of an earlier project which implemented an accelerator but had some limitations. The main areas to have emphasis on are to improve memory traffic time optimization by using DMA (Direct memory access), as well as, to make architecture more generic. Lastly, if time allows, we intend to add software support to make porting CNN architectures easier.

Project Objectives Project Implementation Method

Project is divided into following steps

Benefits of the Project Technical Details of Final Deliverable

CNN accelerator for RISCV ported on FPGA with DMA implementation and improved hardware design.

Final Deliverable of the Project HW/SW integrated systemCore Industry EducationOther IndustriesCore Technology OthersOther Technologies Artificial Intelligence(AI)Sustainable Development Goals Industry, Innovation and InfrastructureRequired Resources
Item Name Type No. of Units Per Unit Cost (in Rs) Total (in Rs)
Total in (Rs) 70000
Zedboard Equipment17000070000

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