contnuous time third order multi bit sigma modulator

Project Title

contnuous time third order multi bit sigma modulator

Project Area of Specialization Wearables and ImplantableProject Summary

Human heart control the functionality of the body, if heart does not function properly, an artificial pacemaker is demanded to correct the heart contraction. The more functionality at a limited power budget requires less power per function. Also power consumption of front-end of pacemaker has to be reduced. An analog-to-digital converter (ADC) in the pacemaker consumes the largest amount of power in the front-end so low power ADC is required. The IECG is a very weak signal (1-5 mV) at very low frequencies ranging from 50mHz to 100Hz.This works proposes to design ADC for Cardiac Pacemaker Implantable System. A continuous-time Third-order multi-bit delta-sigma modulator designed for high accuracy data conversion in implantable devices such as pacemakers biomedical applications. A trade-off of the cascade of integrator with multiple-feedforward (CIFF) and cascade of integrators with multiple-feedback (CIFB) studied for higher loop stability. A multi-bit quantizer is preferred due to higher performance as compared to single-bit quantizer implementation. The power reduction techniques for the loop filter of the modulator are also studied to reduce the power and improve the performance. The oversampling ratio of the modulator increase to meet the small bandwidth requirement. Significant power reduction is achieved by utilizing power efficient amplifier architecture for the integrators in the loop filter of the modulator. Signal transfer function and noise transfer function of the modulator for the continuous time coefficient from the discrete time model of the modulator. The feedback digital-to-analog (DAC) pulse for Non Return Zero (NRZ) utilized for higher performance. The circuit non-idealities of the modulator also simulated like thermal noise, jitter noise, feedback DAC mismatching. The active RC integrators are preferred or gm-C integrator with higher performance. Also the folded-cascode structure of the operational amplifier preferred over telescopic cascaded due to wider output swing. While the operational amplifier for these three integrators have DC gain of 10 M, and gain-bandwidth (GBW) of 100G to suppress the circuit non-idealities. With NTF zero optimization, the modulator can achieve SNR of 71.1 dB at the circuit level and at the MATLAB level it can achieves SNR of 82 dB. The sampling frequency of the modulator is 4 MHz, the modulator can achieve signal bandwidth of 125 kHz.  Finally the complete modulator at the circuit level with input signal at 18 kHz for bandwidth of 125 kHz can achieve SNR of 71 dB at supply voltage of 1 V.

Project Objectives

1. A low power analog to digital converter designed for biomedical applications. The pacemaker requires several analog to digital converter with medium resolution with small bandwidth.
2. The main objective of this project is to build up low power continuous-time delta-sigma modulator ADC for biomedical application in general and specific to pacemaker.
3. To understand and develop the circuit level skill to design circuit for implantable system.
4.  To reduce the power consumption of the power hungry building block inside the ADC, that is operational amplifier.
5. Develop skilled labor.
6. To promote Integrated Circuit (IC) industry in Pakistan.

Project Implementation Method

The modulator will be modeled using MATLAB, using Delsig delta-sigma toolbox.  The ideal modeling will implement ideal integrator with maximum quantization noise attenuation in the delta-sigma modulator.  To simulate the circuit non-idealities using Sigma-Delta Toolbox. The thermal noise, Flicker noise and switched-nonlinearity will be implemented. Also finite gain and limited GBW of the amplifier inside the integrators in the modulator will limit the performance of the modulator. The operational amplifier DC gain plots are provided to understand the effect of the quantization noise attenuation of the modulator. The limited DC gain inside the operational amplifier limits the noise shaping performance of the modulator. Hence the DC gain of the amplifier raised to show the accurate noise shaping. Circuit non-idealities are simulated at the modeling level to check the performance margin at the transistor level implementation. Once get a reasonable performance, an ideal circuit level implementation developed in the circuit simulator Virtuoso Cadence environment. At circuit level performance needs to be checked after several simulation and recover the loss in performance if any circuit level implementation issue.

Once the ideal circuit level implementation successful, then real transistor based circuit replace to the ideal models of amplifier and also ideal resistor and capacitor are replaced with real resistor and capacitor. Further simulations are performance and check more if any issue at the circuit level that may degrade the performance. The last step is after replacing all ideal circuit building block by real transistor based models. The final step to get the performance by simulating thermal noise, feedback mismatch. The final performance should meet the required SNR requirement for the desired signal bandwidth.

Benefits of the Project

1. Economically boost the country with Integrated Circuit (IC) design industry.
2. A successful development of implantable prototype results in Startup company that leads to design IC in Pakistan.
3. This will also cut the imports of the expensive biomedical equipment’s by designing in the country.
4. It will be available locally that will boost the local industry.
5. This will develop local human resource as skilled worker.

Technical Details of Final Deliverable

The complete transistor level circuit implementation of the delta-sigma modulator for pacemaker can achieve SNR of 65 dB and dynamic range of 65 dB for signal bandwidth of 125 kHz with thermal noise, DAC mismatch. The modulator have CIFB architecture for target power consumption of 200µW at supply voltage of 1 V in 28 nm CMOS technology.

Final Deliverable of the Project Software SystemType of Industry Health Technologies Wearables and ImplantablesSustainable Development Goals Industry, Innovation and InfrastructureRequired Resources

Item Name	Type	No. of Units	Per Unit Cost (in Rs)	Total (in Rs)
			Total in (Rs)	80000
Office Chairs	Miscellaneous	2	5000	10000
Smart Devices	Equipment	1	35000	35000
Screen/Monitor	Equipment	1	35000	35000