2x2 MIMO implementation on hardware

Project Title

2x2 MIMO implementation on hardware

Project Area of Specialization Information & Communication TechnologyProject Summary

MIMO (Multiple Input Multiple Output) utilizes elements of multiple antennas to on transmitter and receiver to achieve spatial diversity. A number of techniques has been proposed and validated in simulations to improve the performance of wireless systems. However, validation of those techniques in actual hardware is much more challenging because implementing such a system in hardware takes a significant amount of time, effort and with a high cost. The wireless communication technologies requires expensive testing and implementation facility. For this purpose, a less expensive and flexible alternative can be found in FPGA, which is an active programmable device.

Space time coding has been into considerations from a long time and many advancements have been proposed in implementing the design for better MIMO communication. Space time codes transfer multiple and redundant data from the transmitter to the receiver through multiple antennas so, that it can provide at least some of the data as it is transmitted from the transmitter side.

Currently FPGA approach could help researchers and engineers to solve the hardware problems into software problems.FPGA is a type of device that is used in electronic circuits.It can be programmed or reprogrammed to required functionality after manufacturing.The confirmable logic blocks and interconnect matrix make FPGA a very powerful and flexible technology.Significant amount of signal processing can be conducted in a software.The aim of this project is to implement a particular multi-antenna scheme using FPGA through algorithms of Space Time  Codes which are Space Time Block Code (STBC) and Space Time Trellis Code (STTC).

Project Objectives

This proposed project aims to fulfill the following objectives:

• Creation of MATLAB simulation of a 2 x 2 MIMO wireless communication system using the Space Time codes.
• To implement a 2 x 2 MIMO system with BER estimation.
• Design of hardware implementation of components of 2 x 2 MIMO system on FPGA and writing VHDL code to implement the proposed design.

Project Implementation Method

Benefits of the Project

The need for reliability, speed and quality in the wireless digital communication has lured the interest of vast community of technologist and communication forums to have a look at the multiple-input multiple-output (MIMO) technology. The key advantages of MIMO system are increased reliability obtained through diversity and higher data rate obtained through spatial multiplexing. Our system will provide a solution using FPGA as target platform , for implementing algorithms for transmission of signals using MIMO systems. The aim of our project is to implement MIMO communication system by space time codes on FPGA which is an active programmable device. Our proposed system will provide better data rate and performance than currently used wireless system.

Technical Details of Final Deliverable

Creation of MATLAB simulation of a 2 x 2 MIMO wireless communication system using the Space Time codes.The technique of STBC can be easily expanded to two transmit antennas and N number of receive antennas to provide a diversity order of 2N.Alamouti scheme could be determined by the following three functions.

• the encoding and transmission sequence
• the combining technique at the receiver
• the decision rule for maximum likelihood detector

The second space time code technique is space time trellis code which is implemented using viterbi algorithm. . The Viterbi Algorithm can be simply described as an algorithm which finds the most likely path through a trellis, i.e shortest path, given a set of observations.

Unlike a block code, which has a fixed length ‘n’, a convolutional encoder is basically a finite-state machine. Hence the optimum decoder is a maximum-likelihood sequence estimator (MLSE). Therefore, optimum decoding of a convolutional code involves a search through the trellis for the most probable sequence. Generalized block diagram of system is given below:

Final Deliverable of the Project HW/SW integrated systemCore Industry TelecommunicationOther IndustriesCore Technology OthersOther TechnologiesSustainable Development Goals Industry, Innovation and InfrastructureRequired Resources

Item Name	Type	No. of Units	Per Unit Cost (in Rs)	Total (in Rs)
			Total in (Rs)	50000
FPGA card	Equipment	1	50000	50000